The present invention relates in general to integrated circuits, and more particularly to memory arrays of integrated circuits. Still more particularly, the present invention relates to the stress testing of periphery circuits of synchronous RAMs (Random Access Memories). Memory arrays of synchronous RAM devices are composed of many different circuits which are all necessary to its successful operation. These circuits within a synchronous RAM may include, for example, row decoders, column decoders, write decoders, and various pre-decoding and post-decoding circuits. Stress test modes may be employed to stress the integrity of synchronous RAM memory arrays. A synchronous RAM device may be put into a memory cell stress mode, for instance, in which all the rows and columns of all the memory cells of the device are selected and accessed in order to allow for stressing of the memory cells.
While stress testing of memory cells of synchronous RAMs has thus been accomplished, stress testing of synchronous RAM decoders and other periphery circuits is typically not performed due to the inordinate amount of time such stress testing would require. In order to stress test each gate in the decoders and other periphery circuits, each and every possible address combination must be individually selected and a stress voltage then applied to the device. For example, stress testing of decoders and other periphery circuits of a 1 Meg synchronous RAM, such as a BRAM (Burst RAM), organized as a 128K by 8k memory array would require selecting and then applying a stress voltage for 128,000 address combinations. As is known in the art, a BRAM may be used with a microprocessor and has an internal address counter which will increment addresses when in a burst mode such that the microprocessor does not need to provide an address count to the BRAM. Because selecting and then stressing every possible address combination would be extremely time consuming, stress testing of decoder and other periphery circuits of synchronous RAMs is typically not performed.
An unfortunate effect of not performing stress testing on decoder and other periphery circuits of synchronous RAMs is that latent defects contained within decoder and periphery circuitry are not detected. Thus a manufacturer of synchronous RAMs may unwittingly produce marginal devices having latent defects. Therefore, there exists an unmet need in the art to be able to stress test decoders and other periphery circuits of synchronous RAMs within a reasonable period of time.